Computer Science notes ⇒ Digital and Analogue Circuit Design

It is positional notation, e.g., 3456 = 3 × 10⁴ + 4 × 10² + 5 × 10¹ + 6 × 10⁰. For binary, this could be: 0111 = 0 × 2³ + 1 × 2² + 1 × 2¹ + 1 × 2⁰. 0 + 4 + 2 + 1 = 7.

To distinguish pure binary, you could say it was the 8421 code (from the column weightings).

Everything but the left-hand column is reflected by the mid-point. The left-most column is reflected instead. You repeat moving down each column.

BCD codes can represent the decimal numbers 0-9. Different codes could be:

• 8421 BCD
• 7421 BCD
• 5421 BCD
• 5211 BCD
• 8421 BCD
• Excess-3 BCD
• Grey BCD

In most cases, the names come from the weightings. Excess-3 is where you add 3 to every pure-binary number (8421) to get the Excess-3 BCD.

See Introduction to Computer Systems for more information and parity, Hamming detection and Hamming distance.

Minimum distance is the number of bits that need to be changed to make another valid word.

An SN74LS180 is a device that is a parity generator/checker.

These are called bi-stables, or flip-flops. They are capable of storing 1 bit of data as long as they are powered. Generally, there are two outputs, Q and Q which give opposite outputs. There is also typically a CLK (clock) input and reset lines (which are independant of the clock and are active-low, meaning they float high, and can be left hanging).

The type of flip-flop determines the state to which they switch and the inputs give them their name: SR, D, T and JK.

A step-down transformer can be used with a Zener diode and a Schmitt trigger inverter to generate a clock based on mains voltage (50 Hz). Mains voltage is regulated so that a clock based on it will never be more than a minute out.

Crystals can also be used to create a stable frequency, but long-term drift does occur.

Synchronous

Asynchronous

Gate-level Asynchronous

D	Q(t+1)
0	0
1	1

The value of D is transferred to Q after the clock arrives.

T	Q(t+1)
0	Q(t)
1	Q(t)

The value of T determines whether or not Q should change state (toggle).

J	K	Q(t+1)	Meaning
0	0	Q(t)	no change
0	1	0	reset
1	0	1	set
1	1	Q(t)	toggle

The JK is a general purpose flip-flop.

S	R	Q(t+1)	Meaning
0	0	Q(t)	no change
0	1	0	reset
1	0	1	set
1	1	???	don't use

X	Y	Q(t)	a	b	T	Q(t+1)
0	0	0	0	0	0	0
0	0	1	0	0	0	1
0	1	0	0	1	1	1
0	1	1	0	0	0	1
1	0	0	0	0	0	0
1	0	1	1	0	1	0
1	1	0	0	1	1	1
1	1	1	1	0	1	0

Note: Y is equivalent to J and X to K.

When D-type flip-flops are connected in parallel, inputs are passed from one flip-flop to the other, providing a shifting operation. The shift loses the least significant bit, causing the divide to be rounded down. A 0 must be shifted onto the word for it to work. If you left-shift, you can multiply by 2, but this time, the most significant bit is lost.

A T-type flip-flop has only half the period of the input signal, therefore can be used for dividing by 2. Connected in series will lead to dividing by 2, 4, 8, etc...

By shifting numbers into the shift register, you can then read them off in parallel. For example, if you shift Q₀, Q₁, Q₂ and Q₃ into a 4-bit shift register, you can then read off the values in parallel to get a parallel word of Q₀, Q₁, Q₂ and Q₃.

Because you can use T-types to divide, if you make them asynchronous and put them in serial, you can create a counter. By attaching the T-type to 1, and then using Q to power the clock for all flip-flops after the first one, you can inspect Q for each flip-flop to get a binary word representing the current value in the word.

Then, by combining Q for the first flip-flop with Q for each subsequent flip-flop into a NAND, and then into the CLR circuit, you can reset the counter to prevent overflow.

This is sometimes referred to as a Class A machine.

The outputs are a function of the current state (according to the memory elements) and the inputs, according to the output decoder. The next state decoder determines the next-state to be held in the memory elements. It is assumed there is also a clock for the memory elements.

This is sometimes referred to as a Class B machine.

A Mealy machine is like a class A machine, but the output is only a function of the current state, and not the outside world.

A Class C machine is like a Class B machine, but with no output decoder.

A Class D machine has no outside world inputs, i.e., it is a pure signal generator.

A state diagram is a pictorial representation of the state table.

Present State		Inputs	Next State		Outputs
A	B	x	A	B	y
0	0	0	0	0	0
0	0	1	0	1	0
0	1	0	0	0	1
0	1	1	1	1	0
1	0	0	0	0	1
1	0	1	1	0	0
1	1	0	0	0	1
1	1	1	1	0	0

For the above state table, the state diagram would look like:

The circle shows the current state and the arrow show what transition occurs with that x/y value pair. Note, the values are the values after the transition, when the circuit has become stable.

When designing a sequential circuit, it is necessary to know what inputs are needed to trigger the desired transition (as given in the design). An excitation gives this information, and is kind of a reverse characteristic table.

D-type

T-type

SR-type

JK-type

From the excitation tables from the individual flip-flops, it is possible to create an excitation table for a sequential circuit. The table is broken up into 3 sections: Current state; Next state; and Flip-Flop Inputs. The Current State column lists the state before the clock edge, the Next State lists the state required after the clock edge, and the Flip-Flop Inputs list the inputs each input requires to get that desired Next State.

Although the choice of flip-flops is often out of your control, if you do have a choice over which flip-flops you could use, some are better suited to tasks then others.

• D-type flip-flops are best for shifting operations (e.g., shift registers).
• T-type flip-flops are best for complemention operations (e.g., binary counters)
• JK-type flip-flops are best for general applications (they are the most versatile, and it is the easiest to make the other types out of)
• SR-type flip-flops are safe to use also, as long as the circuit is designed properly, so the 1,1 condition never occurs across the inputs.

Modern flip-flops change on a clock edge. Early flip-flops changed on the pulse itself, which led to difficulties when combining flip-flops into counters and registers.

Switch Debounce

SR flip-flop

Mano p347-348

A race condition is said to exist in an asynchronous sequential circuit when two or more binary state variables change state in a response to a change in input variable. When unequal delays are encountered, a race condition may cause the state variables to change in an unpredictable manner.

If the final state of the circuit does not depend on the order in which the state variables change, the race is called a non-critical race. If it is possible to end up in two or more stable states depending on the order in which the state variables change, this is called a critical race.

Analysis of a transition table can show race conditions, but it does assume 0 gate delay, which is not true. The transition table can not predict the behaviour of a circuit where a precisely timed enable line ensure correct logical behaviour.

If you use a NAND inverter into a SR flip-flop, and then use the spare input, you can make an enabling line. When the enable line is low, S and R can take any input and Q and Q will not change. When the enable line is high, it will behave like a normal SR flip-flop. This enabling mechanism is sometimes called a level-sensitive clock.

If you invert S in the above circuit and connect it to R, you will get an enabled D-type flip-flop, which is a well-behaved circuit called a latch - which is still widely used.

A logical analysis of an asynchronous circuit can be achieved by breaking the feedback links and forming a Karnaugh map. As a Karnaugh map, static hazards can be determined.

Essential hazards occur when an input changes and this is not detected by all the excitation circuits before the state variables are sent back to the excitation circuits.

Early flip-flops had enabling/disabling clocks - these were called level-sensitive. Although early SR and D-types were well behaved, the T and JK types required the enabling clock pules widths to be precisely set for each flip-flop.

The basic enabling clock pulse made D-type flip-flops connected in a shift register difficult to be controlled. The pulse duration had to be shorter than the input-ouput delay of the flip-flop.

Modern flip-flops are synchronised on the edges (transitions) of the clock, not the pulses (levels). There are three basic mechanisms for implementing this - edge-triggered, master-slave and master-slave with data lockout - and they are either positive edge clocking (on the rising edge) or negative edge clocking (on the falling edge). Once the clock has passed the threshold, the inputs are locked out and is unresponsive to changes on the input. There are finite times when the inputs must not change. These are:

• Setup time (t_su) is the time for input data to settle in before the triggering edge of the clock occurs. Typical value is around 20 ns, but in reality this is shorter.
• Hold time (t_h) is the time required for the input data to remain stable after the triggering edge of the clock occurs. Typical value is around 5 ns, but in reality this is shorter.

In a manufacturers data book, minimum values are specified, which is the shortest intervals for which correct operation is guaranteed.

The propogation delay of a flip-flop is defined as the time between the clock reaching the clocking threshold (the transition point) and the outputs responding to the flip-flop inputs as they were, immediately before the clock acheived the threshold.

Master-Slave Flip-Flops

Synchronous circuits which are controlled by asynchronous inputs may cause flip-flop inputs to change during setup and hold periods - such changes may cause an inappropriate jump in sequence. It is important to synchronise the asynchronous inputs so they do not occur during setup and hold times - this is acheived by latching (with a latch) or registering (with a register) the inputs.

When the input changes during the flip-flops setup time, metastability can become a problem. The output is unstable for some time before it settles to a stable state and the output level can be halfway between 0 and 1 and be recognised inconsistently as either 0 or 1. The length of time the output is metastable is unpredictable.

A flip-flop is limited in speed by the switching times of the transistors that make up the flip-flop. The speed of the clock is determined by such factors as: the propogation delay of the flip-flop, the propogation delay of the next-state decoder and the setup time of the flip-flop.

Maximum Flip-Flop Clocking Frequency

Minimum Flip-Flop Pulse Duration

Races in Synchronous Circuits

In a synchronous sequential circuit, all flip-flops are supposed to be clocked at the exact same time. If this does not happen, it causes clock skew. Clock skew can be caused by:

• unequal gate delays in clock buffers
• unequal wire length
• unequal clock threshold voltage

A small amount of clock skew is tolerable, however. To determine the clock skew tolerance, the minimum flip-flop propogation delay needs to be known, but this is not always given in manufacturer's data sheets. The guaranteed minimum setup time (the actual will probably be less) also needs to be known. For master-slave devices with data lockout, the effective allowable clock skew is the minimum propagation delay minus the setup time plus the clock pulse width. Thus, the designer can set the maximum allowable clock skew needed by changing the pulse width.

An SRAM cell looks like:

A bank of cells forms RAM. In an 8 bit word, 8 cells are in parallel, and a decoder selects which line to read.

Memory Address Decoding

A 64 k 1-bit DRAM is physically constructed as a 256 × 256 array of bits. 16 bits of address are needed to address the 1-bit word. The address is presented as 2 8-bit words in sequence requiring a row address strobe (RAS) and a column address strobe (CAS). To refresh, the RAS line is made high, the address is stored and the whole row is stored in a 256-bit latch. Then RAS goes low and the row is written back from the latch.

In the read cycle, a row is specified and stored in the 256-bit latch. A column is then read and stored in the column address register. A multiplexer is then used to select 1 bit from the row latch which is made available at the output. The row address strobe goes low and the row is written back.

In the write cycle, the row is addressed and stored in the 256-bit latch. WE (Write Enable) is asserted and then CAS is asserted. The bit on the input line is read into the 256 bit latch (using a demultiplexer) using the column address register and the latch is written back into the array when the row address strobe falls to zero.

It is possible to read/write part or all of a row before the writing back process occurs.

Normally if A-B, the magnitude of B is converted to its two's complement and added to A. If the msb of the result is 1 then the result must be two's complemented to obtain the magnitude of the negative number.

We can create a half-adder by truth table analysis:

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

So, Sum = A XOR B and Carry = AB.

A full adder needs to consider the previous carry bit when adding, so this gives us a new truth table:

A	B	Ci-1	Sum	Carry
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

We can conventionally minimise this, but another solution is to write it out in the canonical form and use boolean algebra. Using this, Sum = A XOR B XOR C_i-1 and carry = AB + (A XOR B)C_i-1. Therefore, we can implement a full adder using two half-adders (XOR's can only have 2 inputs, so we need to chain them).

Although this is the standard textbook design of a full adder, due to constaints with the speed of the carry, they aren't really implemented like this. A full-adder is deduced using map factoring (Karnaugh maps and some intuition), which is likely to be less hazardous due to lots of looping.

A 4-bit binary adder uses parallel binary adding, with the adders connected in serial. However, the correct addition of a bit depends on the states of the carry bits before it - leading to a "ripple effect" of carry bits being computed and the correct answer propogating through. This ripple effect determines the operational speed.

We should use look-ahead carry to increase the speed of our adder.

The look-ahead carry provides parallel generation of each carry bit at the expense of additional gates. The sum function for the full-adder remains the same, but the carry function is reconsidered.

Two carry bits are needed, a generate and propagate:

• G = AB
• P = A XOR B

So the carry function becomes: C = G + PC_i-1 and the sum function becomes: S = P XOR C_i-1. Both of these terms can be generated using half-adders.

Subtraction uses two's complement. By using XOR gates and a mode line connected to the gates and C_in you can invert the inputs and then add 1, giving you the numbers in 2's complement. By setting the mode line to 0 normal addition can still occur on the same gate.

Truth table analysis would give us an expression for the subtractor which can then be used to construct a circuit.

A comparator compares two binary words for equality. Most also provide arithmetic relationships between them - i.e., outputs indicating greater than or less than. Generally the arithmetic output assumes the words only represent a magnitude.

ALUs are covered
in CAR and ICS

Arithmetic Logic Units provide arithmetic and logic operations on a pair of words.

XORs into a NOR gate or XNORs into an AND gate provide an equality test.

If you realise an XNOR in 5 gates, you can also extract greater than and less than from the internal nodes, as well as equality from its output.

Comparators (SN74LS85) can be chained, so they normally have 3 additional inputs: AGTBIN, ALTBIN, AEQB, which are taken into account when a comparison is done.

ALUs come in different sorts, and provide different operations on the inputs depending on what is needed of them. For example, the SN74LS181 provides a 4 bit function selector and a 1-bit mode selector that allows it to choose between logic or arithmetic mode.

ALUs can be cascaded, so they often have additional inputs such as CIN (carry in), P and G (carry propagate and generate) and COUT (carry out).

One way of doing integer multiplication is repeated addition, e.g., 3 × 4 = 4 + 4 + 4. You should select the smaller number to minimise the number of adds, and this is implemented using a sequential circuit. Another way of implementing this is using shifting and adding. m bits numbers require m shift-and-add operations. This is also a sequential circuit. The final implementation method is by designing a combinatorial circuit that accomodates all possible combinations of inputs.

If the maximum bit size for unsigned integers is n bits, then 2n bits are required to store the results. If negative numbers are to be accomodated, then 2n+1 bits are needed.

To do repeated addition, feedback from an adder is used for one word and then the other word is the other input from an adder. A down-counter connected to inhibit the clock when it reaches 0 is used to control the number of additions.

Shift-and-add is similar, but a shift register is used to control the adding process, and the second word is also attached to a shift register. If negative numbers are to be handled, then the registers and adder must be n+1 bits wide.

Standard combinatorial logic can be used to create a combinatorial multiplier. Combinatorial multipliers can also be chained together. For example, you can create a 4 × 4 multiplier with 4 2 × 2 multipliers like so:

A × B = (A_LSB × B_LSB) + 2((A_LSB × B_MSB) + A_MSB × B_LSB)) + 4(A_MSB × B_MSB)

Array based multipliers, which is based on the AND gate can also be used. Here, half-adders and full-adders are combined to cascade the output for multiple-byte addition. Array-based multipliers can be combined in a building block for VLSI replication.

For division, negative numbers are normally converted to unsigned, and then the final sign is figured out by rule. One method of division is to keep subtracting the divisor from the dividend until the result of the subtraction is negative - the number of repetitions less 1 is the quotient. To the negative result, you then add back the divisor to obtain the remainder.

Given that a fast multiplier may already exist, it is possible to consider an approach based on it. dividend = (divisor × quotient) + remainder. The quotient is set to 0, and then increment, multiply the quotient and divisor, and if the result is greater than the divided, stop and decrement the quotient for the correct answer.

You can also use restoring division, based on shift and subtract, except when the subtraction results in a negative number, the divisor must be added back.

Non-restoring division is similar, except that when the subtraction results in a negative number, the divisor is shifted and added. This results in n additions, compared with an average of 1.5n additions for the restoring divisor. This is a fast, sequential process.

Combinatorial dividers exist which offer parallel division, but there are not covered.

Electricity is an energy supply that is convenient to produce, distribute and use. Emf (Electromotive force) causes electric charge to flow. Charge (Q) is the measure of the surplus or deficit of of electrons and is measured in Coulombs. The smallest amount of charge possible is the charge on an electron (1.6 × 10^-19 C) which is denoted with the symbol e.

Electric current (I) is the rate at which charge flows (I = dQ/dt). Current can only flow in closed paths, so we speak of electric circuits. A useful electric circuit consists of at least one device that produces a desired effect and an energy source that can maintain a current throughout the circuit.

The fundamental quantities to be found in electric circuit analysis are voltage (V) and current (I). These two are related, since the voltage across a device drives a current through it, or a current through a device generates a current across it.

Potential difference is the work (measured in Joules (J)) required to move a unit of positive charge (1 C) between two points - E = QV. It is a measure of the force which tends to move charge from one point to another. Potential difference relative is ground (0 V) is often just called potential. Emf is the potential difference from a voltage source, such as a battery.

In conductors, charge can move easily. In insulators, charges can't move easily.

Ohm's Law states that the potential difference across a conductor is proportional to the current through it. The constant of proportionality is called resistance (R) and is measured in Ohms (Ω). This gives us V = IR.

Resistors are used for voltage to current conversion, or vice-versa. They are rated for their ability to dissipate power. The inverse of resistance is called conductance (G) and is measured in Siemens (S). This gives us V = I/G.

We know that E = QV, however if we measure change across time, then V is a constant and dE/dt = dQ/dt V. We know that power is the change in energy over time and current is the change in charge over time, so we can derive that P = IV. This is measured in Watts (W) or Joules per second (Js^-1).

As we mentioned earlier, some kind of power source is required for the circuit to be useful. In circuit analysis, it is often convenient to think about idealised energy sources.

An ideal voltage source is independant of the current passing through it and an ideal current source is independant of the voltage across it.

Real sources are modelled as ideal sources in combination with a resistance, called the internal resistance.

Kirchoff's First (Current) Law

Kirchoff's Second (Voltage) Law

If we move Q Coulombs of charge between 2 uncharged conductors, the voltage difference, V, between the two conductors is proportional to Q such that Q = VC, where the constant of proportionality is called the capacitance of the conductor arrangement. It depends on factors such as the shape and size of the conductors and the material or dielectric between them. Capacitance has units in Farads (F), but typical circuit values are in the microfarad (µF) range or smaller.

From Ohm's Law, we can derive that I = C dV/dt.

If, in a coiled conductor, current is changing with time, it generates a magnetic field which is changing with time. This induces a voltage across the coil itself with tends to oppose the current. The voltage is proportional to the rate of change of current such that V = L dI/dt. This constant of proportionality (L) is called inductance and it is measured in Henry's (H). This is symmetrical to the formula for capacitance, and in ac circuits we find that inductance has the opposite effect to capacitance.

For circuit analysis, it is often convenient to convert from a star arrangement of resistors to a delta arrangement, or vice-versa. Any star equivalent resistor is given as the product of the two delta neighbour resistors divided by the sum of all three delta resistors.

From this, we can derive the equation R₁ + R₂ = R₁₂(R₁₃ + R₂₃) / (R₁₂ + R₁₃ + R₂₃). Similar equations can also be derived for R₁ + R₂ and R₁ + R₂ so simultaneous equations can be used to solve the equation for a particular resistor.

For star-delta transformations, we can manipulate algebraicly our existing equations to give us:

• R₁₂ = R₁ + R₂ + R₁R₂/R₃
• R₁₃ = R₁ + R₃ + R₁R₃/R₂
• R₂₃ = R₂ + R₃ + R₂R₃/R₁

Any delta equivalent resistor is given as the sum of the two star neighbour resistors added to a number which is their product divided by the remaining non-neighbour resistor.

Thevenin's theorem is a circuit reduction technique particularly useful when one only needs to know the state of a specified branch of the circuit (i.e., the voltage across and current through the branch)

Any two terminal (resistive) network can be represented by an equivalent circuit consisting of a voltage (V_t) in series with a resistance (R_t), where V_t is the open circuit voltage and R_t is the Thevenin resistance - the resistances between the terminals with all energy sources removed (voltage sources short circuited and current sources open circuited). Thevenin resistance is measured as R_t = V_OC / I_SC

This is a dual of Thevenin's Theorem - here, a current source and a resistance is used in parallel to represent a two-terminal resistive network.

According to Norton's Theorem, any two terminal (resistive) network may be represented as an equivalent circuit consisting of an ideal current source, I_n, and a parallel resistance, R_n, where I_n is the short circuit current between the terminals and R_n is the same as defined in Thevenin's theorem.

In any linear network containing more than one source of voltage or current, the current in any element in the network can be found by determining the current in that element when each source acts alone and then adding the results algebraically.

By finding the voltage at an unknown node, then you can figure out all voltages and currents in the circuit based on that. Kirchoff's Current Law is used to find out the missing voltage.

From Wikipedia, the method is:

1. Label all the nodes in the circuit (e.g. 1, 2, 3...), and select one to be the "reference node." It is usually most convenient to select the node with the most connections as the reference node.
2. Assign a variable to represent the voltage of each labeled node (e.g. V₁, V₂, V₃...). The values of these variables, when calculated, will be relative to the reference node (i.e. the reference node will be 0V).
3. If there is a voltage source between any node and the reference node, by Kirchoff's voltage law, the voltage at that node is the same as the voltage source's. For example, if there is a 40 V source between node 1 and the reference node, node 0, V₁ = 40 V.
4. Note any voltage sources between two nodes. These two nodes form a supernode. By Kirchoff's voltage law, the voltage difference at these two nodes is the same as the voltage source. For example, if there is a 60 V source between node 1 and node two, V₁ − V₂ = 60 V.
5. For all remaining nodes, write a Kirchoff's current law equation for the currents leaving each node, using the terminal equations for circuit elements to relate circuit elements to currents. For example, if there is a 10 Ω resistor between nodes 2 and 3, a 1 A current source between nodes 2 and 4 (leaving node 2), and a 20 Ω resistor between nodes 2 and 5, the KCL equation would be (V₂ − V₃)/10 + 1 + (V₂ − V₅)/20 = 0 A.
6. For all sets of nodes that form a supernode, write a KCL equation, as in the last step for all currents leaving the supernode, i.e. sum the currents leaving the nodes of the supernode. For example, if there is a 60 V source between nodes 1 and 2, nodes 1 and 2 form a supernode. If there is a 40 Ω resistor between nodes 1 and the reference node, a 2 A current source between nodes 1 and 3 (leaving node 3), and a 30 Ω resistor between nodes 2 and 4, the KCL equation would be (V₁ − 0)/40 + (−2) + (V₂ − V₄)/30 = 0 A.
7. The KCL and KVL equations form a system of simultaneous equations that can be solved for the voltage at each node

This uses simultaneous equations, KVL (but not KCL), and Ohm's Law to determine unknown currents in a network. The first step is to identify "loops" within the circuit encompassing all components and then envisioning circulating currents in each of the loops (the loop direction is arbitary, but the equations are easier if all loops are circling in the same direction). A more formal method from allaboutcircuits.com follows:

1. Draw mesh currents in loops of circuit, enough to account for all components.
2. Label resistor voltage drop polarities based on assumed directions of mesh currents.
3. Write KVL equations for each loop of the circuit, substituting the product IR for E in each resistor term of the equation. Where two mesh currents intersect through a component, express the current as the algebraic sum of those two mesh currents (i.e. I₁ + I₂) if the currents go in the same direction through that component. If not, express the current as the difference (i.e. I₁ - I₂).
4. Solve for unknown mesh currents (simultaneous equations).
5. If any solution is negative, then the assumed current direction is wrong!
6. Algebraically add mesh currents to find current in components sharing multiple mesh currents.
7. Solve for voltage drops across all resistors (E=IR).

Arithmetic operations on complex numbers are consistent with those on reals:

• (a + bj) + (c + dj) = (a + c) + (b + d)j.
• (a + bj) - (c + dj) = (a - c) + (b - d)j.
• k(a + b)j = ka + kbj.

This is similar to the way vectors work. Indeed, complex numbers can be represented as vectors on an Argand diagram.

The operator × j can be interpreted as a 90 degree clockwise rotation. e.g., j(2 + j) = -1 + 2j.

Additionally, j⁴ = 1.

As our complex numbers are vectors, we can represent them in polar form. z = a + bj = r(cosθ + jsinθ). If we use Taylor expansions, we can break this down to e^jθ = cosθ + jsinθ. Thus, e^jθ is a unit circle on the Argand diagram and a general complex number, z can be written as re^jθ.

When adding and subtracting complex numbers, the Cartesian form must be used. When multiplying or dividing, either form can be used, but the polar form is more convenient.

An ac signal (voltage or current) changes magnitude from instant to instant. Sinusoidal quantities can be conveniently represented using rotating vectors called phasors. Linear circuits with energy sources at a given frequency have all voltages and currents oscillating at that frequency. We can use a phasor diagram that disregards frequency information and captures the phase and magnitude information only.

By convention, phasors rotate anti-clockwise, so if a phasor has a positive j, we say it leads by the given angle and if the phasor has a negative j, it lags by the given angle.

To discover the phasor of v, we can use KVL, so v = V_R + V_C + V_L. These are vector quantites, so they must be added vectorly (e.g., using a vector diagram). In this circuit, we chose current to be the reference, as it is a series circuit and the same current flows through all 3 elements. The voltage across each element is different in voltage and phase, due to their different impedances. The phasor diagram then shows the phase relationship between the voltage and current. In this case, the current lags behind the voltage, as the inductive reactance is larger than the capacitative reactance.

As we know from complex numbers, we can represent an ac quantity by the phasor Ae^jΦ, and this encapsulates both the magnitude (A) and phase (Φ) information.

Now we have removed the dependance on time from our calculations, ac circuit calculations can be done with apparantely constant quantities, e.g., reactance calculations.

• V = IZ, hence
• Z_R = R and also
• Z_C = -j/ωc (= 1/jωc)
• Z_L = jωL

Impedance (Z) is the resistance to the flow of ac currents (the inverse of this is admittance, Y). Z may include:

• a non-frequency dependant part, called resistance (R). The inverse of this is conductance, G.
• a frequency dependant part called the reactance (X). The inverse of this is the susceptance, B.

V/I = Z = R + jX.

In general, X (a reactance) e.g., X_C = 1/ωC and X_L = ωL and ±jX is an impedance with 0 resistive component, e.g., Z_C = -j/ωc and Z_L = jωL.

Thus, resistances and reactances deal with magnitures, whereas impedances capture magnitude and phase.

From Ohm's and Kirchoffs laws, we can derive that series combination works such that Z_S = Z₁ + Z₂ + ... and parallel combination works such that 1/Z_P = 1/Z₁ + 1/Z₂ + ...

Often, we need to consider the behaviour of a circuit in the frequency domain, rather than the time domain, e.g., filters, resonant circuits, etc...

Any signal can be generated by the summation of sinusoids. These signals can be seperated using a filter (e.g., noise from a signal can be removed to isolate a particular frequency)

In the above filter, the filter gain is V_O/V_I

Low pass filters can clean up a noise contaminated signal after it has passed through a transmission medium. A high pass filter can remove DC between stages of transistor amplification, so transistor biasing is not affected.

Band pass filters can be employed which only allows signals of a particular frequency through.

The effectiveness of filters can be shown by a graph of frequency against gain. Ideal filters of different types and a more realistic filter graph are shown below:

cos(ωt) → filter → G cos(ωt + Φ)

The system behaviour depends on frequency because reactances depend on frequency. This behaviour is known as frequency response. The frequency response can be measured by varying the frequency of the input signal and measuring the amplitude and phase of the output signal with regard to the input signal in steady state. The magnitude of the voltage gain, G, and phase difference Φ can be plotted as a function of frequency to describe the behaviour of the linear circuit.

Frequency and gain (but not phase) can vary over huge ranges, so we use logarithmic scales to represent these. A multiple of 10 of frequency is called a decade (similarly, a multiple of 2 is called an octave in music).

log₁₀P is power P expressed in bels, however as this scale is very course, we use decibels (a tenth of a bel). 1 dB is 10log₁₀P, which is power P represented in decibels.

As P is proportional to V², 20log₁₀V gives the voltage gain in decibels (derived from logarithmic laws, 10log₁₀V² = 20log₁₀V.

0dB represents a unity gain (gain of 1) and negative dB represents attenuation. Gain can also be a phasor, G = V_o/V_i, therefore we can derive that G = Ge^jΦ/e^j0, therefore G = Ge^jΦ, where Φ is the phase shift relative to the input.

A Bode diagram is a method of representing frequency response. A Bode diagram plots gain and phase shift against f on two seperate diagrams. They are intuitive and easy to draw.

Since impedances are complex functions of frequency, a filters' behaviour can be described by a complex function of frequency. At certain frequencies (0 and ∞), the passive RC filters' gain and phase tends towards certain values (asymptotes). Constructing the Bode diagram requires drawing the asymptotes in a systematic manner.

If we take a simple example of a filter (V_o/V_i) we have a simple transfer function (from the voltage divider). This gives us V_o/V_i = 1/(1 + jωT).

We can find the asymptotes in the plot by finding where ωT << 1 and ωT >> 1. ωT << 1 ⇒ | V_o/V_i | ≈ 1, hence G_dB ≈ 0 dB. ωT >> 1 ⇒ | V_o/V_i | ≈ 1/ ωT, hence G_dB ≈ -20log₁₀(ωT)

In this case, if frequency increases by a factor of 10, then log₁₀(ωT) increases by 1, hence gain decreases by 20 dB - hence for sufficiently large frequencies, we have a slope of 20 dB per decade.

We also need to find the point where the two asymptotes meet - this is called the breakpoint. For first order low pass filters, the breakpoint defines the bandwidth of the filter. If Z_c = 1/jωC, there may be no breakpoints. In our example, the breakpoint is where neither ωT << 1 and ωT >> 1.

For our sample Bode diagram, we can plot:

For the phase plot, we can also consider the cases at the asymptotes, which gives us Φ ≈ 0° for ωT << 1, Φ ≈ -90° for ωT >> 1. At the breakpoint ωT = 1, Φ ≈ -45°, so the phase plot looks as follows:

A mechanical example of a resonant circuit is a mass on a string (pendulum) that osciallates at a natural frequency (dependant on factors such as mgh) regardless of the force exerted. In this example, energy is repeatedly transformed between different forms (gravitational potential and kinetic, with a small amount of heat from friction) - this is typical of resonant circuits.

In resonant electrical circuits, energy is transferred between the electic field of a capacitor and the magnetic field of an inductor. The energy that is taken from the supply and transferred to heat is dependant on the resistance. The peak amplitude is dependant on the circuit resistance, which is analogous to the effect of friction on the mechanical system.

Sometimes resonance is to be avoided, particularly in mechanical systems, where it can be a destructive force. Other times, it is desirable, such as in frequency selective or tuned circuits. In practice, such circuits can be considered as narrow bandpass filters. The higher and narrower the peak in the response, the better the frequency selectivity. Selectivity depends on the resistance in the circuit, and this is referred to as the Q factor.

Rectifiers

Diode Clamps

Zener diodes have similar characteristics to normal diodes, except they are designed to start conducting at a specific voltage in reverse bias. Thus, when they are reverse biased, they can create a constant voltage in a circuit, derived from a higher voltate in a circuit. This process is called regulation, and this can be easily quantified and measures how the output voltage changes for a given change in input and how much dampening occurs. An ideal Zener diode has a regulation of 0 and has the following V/I characteristic graph:

A FET takes virtually no current into the gate and the drain-source current is controlled by the gate-source voltage.

BJTs have a larger gain than FETs, so BJTs are usually used for simple single stage amplifiers. However, the FET operates with no forward biased functions, so no gate current is needed. FETs are much easier to use than BJTs. They have extremely high impedances, so no base current is needed.

In JFETs, the GS junction should be reverse biased to prevent conduction. For MOSFETs, there is no junction. The gate can be positive or negative with regards to the source.

The drain voltage of FETs are more nearly constant than the collector currents of BJTs for varying the voltage across the drain-source/collector-emitter. Additionally, unlike a BJT, a FET can be made to behave like a voltage controlled variable resistor.

In a BJT, a small base current flows, which controls the larger collector-emitter current.

The V-I characteristics of a BJT collector varies according to I_B, as the following graph shows:

In an ideal transistors, the lines would not be curved, and would be straight across.

The transistor is approximately a controlled current source, but where is the output? If you pass the collector current through a resistor, the voltage drop across the resistor is proportional the the collector current, giving the voltage amplification that is needed.

Applying KVL to the circuit gives us V_CC = I_CR + V_CE, or I_C = -V_CE/R + V_CC/R. Using this, we can apply y = mx + c, where x = V_CE and y = I_C, so it can be plotted onto the characteristic graph above. This is called the load line, and has a slope of -1/R and crosses the axis at V_CC/R. The load line is defined by setting appropriate valyes of V_CC and R. As I_B varies, the instantaneous values of voltage and current for the transistor collector-emitter slide up and down the load line.

• Q_C is the cutoff point, where there is 0 collector current (no base current supplied)
• Q_S is the saturation point, the maximum transistor current, with the collector a tenth (or so) of a volt above the emitter
• Q_O is the operating point, working point, or the quiescent point. The region of the load line around this point is called the active region, where the best amplification can be achieved.

The first two states are extreme states, which are important when transistors are used as switches (i.e., in digital electronics, where the aim is to get it to switch between the two extreme points as quickly and as efficiently as possible). In analogue electronics, the active region is important.

This circuit gives an output that is 0.6 V lower than output, and clipping occurs when V < 0.6. This circuit has a high input impedance, so it is useful as a buffer. They are most commonly seen as in the second diagram, where R₁ and R₂ set the biasing point and the capacitors remove any dc noise that may be introduced into the circuit.

In this circuit, V_O/V_I = -R_C/R_E

On the above I/V plot, for sufficiently high values of V_DS, the characteristic is nearly horizontal and so only has a small dependence on V_DS. However, the value of I is dependent on V_GS. This makes the device a voltage controlled current source/sink.

If we want to produce a device that amplifies a voltage signal, we pass the DS current through a resistor connected to the drain of the FET. The output voltage must lie on a load line which is obtained from an application of KVL:

I = -V_DS/R + V_DD/R

The straight line formula (y = mx + c) can be applied, where y = I, m = -1/R, x = V_DS and c = V_DD/R.

The load line can be defined by setting appropriate values of V_DD and R, then, as v_GS varies, the instantaneous values of voltage and current for the transistor drain-source slide up and down the load line. When no signal is applied to the circuit, V_GS must be biased to be roughly in the centre of the load line.

Rather than manually biasing a transistor, it is often simpler and more elegant to use self-biasing schemes, e.g.,

• JFET (n-channel) biasing - the GS junction is reverse biased. AC couple the input and put a resistor between the gate and ground. DC current through the source resistor sets the appropriate V_GS.
• MOSFET (as with BJTs) requires a divider from the drain supply. Gate biasing resistors can be large (> 1M Ω), because the gate current leakage is so small (in the nanoamps).

Small signal analysis involves modelling the transistor as an ideal voltage source of g_mv_gs in parallel with resistance r_d.

Current is a function of the gate-source and drain-source voltage and the change in current can be expressed as di = δi/δv_GS + (δi/δv_DS)δv_DS. For small signals, we can write i = g_mv_GS + (1/r_d)v_DS, where the transconductance g_m and drain resistance r_d are marginally depedent on the operating point.

When analysing transistor circuits, we consider DC and AC seperately. DC values are indicated by upper case symbols and small signal AC values are indicated by lower case symbols. We consider DC first and get the biasing right, since AC properties have a small dependence on the position of the operating point in the transistor characteristic. We may then examine the transistor characteristic and the circuit diagram to determine AC behaviour, represented by the small signal model. DC sources are shorted to ground to form the small signal model.

The ideal op-amp has characteristics such that:

• Gain A_v is infinite
• Bandwidth is infinite
• Input impedance is infinite
• Output impedance is zero

From these ideal properties, we can infer the following principles:

1. In a negative feedback arrangement, the output attempts to do whatever is necessary to make the voltage difference between the inputs 0
2. The input draws no current

Ideal properties are often used in circuit design and analysis, but they should be justified in relation to other values in the op-amp circuit.

According to our ideal rule 1, the non-inverting input is earthed, so the inverting input must be at the same voltage (0 V). This point is referred to as a virtual earth. Using rule 2, the current into the inverting input is 0, hence applying KCL, we have: v_i/R₁ + v_o/R₂ = 0, which can be rearranged to give v_o/v_i = -R₂/R_1.

The previous expression can be generallised by replacing the resistances with impedances and replacing them, for example, with filters.

Here, v^- = R₂/(R₁ + R₂) × v_o. The ideal op-amps means that v^- = v⁺ = v_i.

From the basic equation v_o = A_v(v⁺ - v^-), we can see that any signal v_i = v⁺ - v^- will almost immediately send the output into positive or negative saturation (i.e., close to one of the supply voltages). Thus, in linear applications, the op-amp is used in a negative feedback configuration.

Negative feedback is the process of coupling some of the output of the system (v_o) back to the input (v^-) to cancel some of the differential input (v⁺ - v^-). If we use greater amounts of negative feedback, the circuit characteristics become less dependent on the open-loop characteristics of the ampifier and more dependent on the feedback network itself. Thus, in the ideal op-amp analysis, circuit properties are defined by input and feedback circuit elements only.

The open loop gain is when there is no feedback. When we do have feedback (normally through a network of resistors), we have closed loop gain. Closed loops give us constant gain up to the bandwidth limit. You need to take care when designing a circuit to ensure that the gain is in the graph area.

The unity gain bandwidth, f_T, will be quoted for a specific op-amp. This is the frequency when the gain drops to unity and is also called the gain-bandwidth product.

The closed loop gain of the inverting amplifier circuit begins dropping when the open loop gain approaches R₂/R₁. This means if we have set R₂/R₁ to give a gain of 100, this gain may be limited by the open loop gain of the op-amp above 50 kHz. Indeed, for all amplifying/filtering applications, we must design inside the open-loop characteristic.

Parameter	Ideal values	Typical real values (for a 741 opamp)
Open loop gain	∞	105
Gain-bandwidth product	∞ Hz	1 MHz
Input impedance	∞ Ω	1 MΩ
Output impedance	0 Ω	100 Ω

For a non-ideal op-amp, we can generalise resistances to impedances and add in the effects of finite input impedance and non-zero output impedance to the inverting amplifier circuit.

KCL can be applied at the inverting input and if we assume that the current taken by the load is negligable, we can apply KCL at the op-amp output. We can cancel out the value of v^- and then if we have a much larger impedance at Z_i then at Z₁ and a much smaller magnitude at Z_o then at Z₂ we can get a formula for the gain: v_o/v_i = AZ₂/(Z₁(A + 1) + Z₂) = -Z₂/(Z₁ + (Z₂ + Z₁)/A). If we have a very large A compared to |(1 + Z₂/Z₁)| we can further generalise to v_o/v_i ≡ -Z₂/Z₁. So we can apply ideal analysis to an op-amp inverting circuit, as long as:

• A >> |(1 + Z₂/Z₁)|
• |Z_i| >> |Z₁|
• |Z_o| << |Z₂|

Filters seperate signals of different frequencies by attenuating signals of all unwanted frequencies. They are often used to remove noise, which is present at all frequencies. To maximise the signal-noise ratio (SNR), we restrict the bandwidth of a circuit to the minimum necessary to allow the frequencies contained in the signal to pass and to filter all the other frequencies. An ideal filter is the "brick-wall" filter of rectangular shape, which is not realisable in practice.

Depending on the application (which has a given accepted and rejected frequency separation) we require the cut off to have a given steepness of slope. The corner should be as sharp as possible, i.e., rapid transition from pass-band to roll-off.

Simple passive RC filters produce gentle roll offs of 20 dB per decade. If a steep roll-off is required, we could cascade multiple low-pass filters. However, passive filters give us quite heacy dampening (ξ). Comparing the equation for cascading passive filters with the standard second order equation shows us ξ = 1, therefore Q (the quality factor) = 0.5, giving a large dampening and a "soft knee" in the frequency response.

We've already looked at LC resonance response, so we can use LC filters to reduce the dampening and give a sharper knee to the filter. By cascading LC(R) filters, we can have arbitarily steep falloff and corner sharpness, but a large number of components are required and inductors are bulky, expensive and can pick up interference (e.g., mains hum).

An op-amp with R and C elements can simulate the behavior of an LCR filter. Such a filter is called an active filter. Furthermore, due to the large input impedance and low output impedance of op-amps, loading problems experienced with cascaded passive filters are removed.

Sallen-Key Filter

In linear applications, negative feedback pre-dominates. Even if some positive feedback is used, negative feedback must dominate for stability, the exception being sine wave oscillators, which are on the cusp between stability and instability and postive and negative feedback are perfectly balanced.. In non-linear applications, we may have no feedback (for comparators), or positive feedback (oscillators and Schmitt triggers). Here, the output switches to close to the power rails. It is important to note we can not assume v⁺ = v^- for these applications, as negative feedback is required to enforce this condition.

The comparator is used to determine which of two signals is larger, or to know whether a signal has exceeded a predetermined threshold. Ordinary op-amps are frequently used as comparators, but a slow slew rate gives a relatively long switching time (20 µs for a 741) due to stabilising internal compensation. The 748 op-amp has no internal compensation and a switching time of less than 1 µs, which is still too slow for many logic circuits.

The 311 comparator has a single rail supply and an open collector output (hence requiring a pull up resistor). This is an example of a special IC that are intended to be used as comparators and can move in and out of saturation much faster. However, comparators chips can not be used in the place of an op-amp, as they can be unstable in negative feedback arrangements due to a lack of compensation.

A simple comparator circuit has a slow output swing and multiple triggering, which is very bad for sequential logic, such as counters.

Connecting R_f introduces positive feedback and introduces dual thresholds, one for each output state. Positive feedback also gives us faster triggering. The resulting hysteresis ΔV is given by ΔV = R₁/(R₁ + R_f)V_pp, where V_pp is the peak-to-peak voltage change.

This is called a Schmitt trigger, and a graph showing the difference between a Schmitt trigger and a standard comparator is as follows:

Op-amps can use positive feedback to generate signals (sine wave, square wave, sawtooth, triangle, etc) which can be used to drive electronic circuits.

As mentioned earlier, we can make an oscillator based on a Sallen-Key filter with K = 3.

The above diagram is that of a Wien-Bridge oscillator, which is popular for generating audio frequencies. The frequency generated is 1/2πRC.

Charging and discharging an capacitor between two threshold voltages combined with a comparator op-amp gives us a relaxation oscillator.

By changing the values of the resistors, you can weight each bit given its place weighting and the outputs are summed using an analogue adder (an opamp). These are difficult to fabricate on ICs due to difficulties in fabricating resistors with an exact value of R, but it is easier to make identically matched ones. Hence, DACs employing an R-2R ladder network are used.

This circuit transforms binary scaled currents to an output voltage. The resistors must be precisely matched. It outputs 0 V for 0 binary input and -150/16 V for a maximum binary input of 15.

Analogue signals vary continuously with time. When converting an analogue signal to a form that can be used by a computer, we require a digitsed, discrete time signal. The signal is sampled at a given frequency to give us a discrete time signal. The discrete time signals are digitised, i.e., they are represented by a fixed number of bits and so are quantised representations of the original analogue signal. The diagram below is an example of such a "sample and hold" waveform.

Nyquist Sampling Theorem

Quantisation Error

Several different types of ADCs are available and the correct choice depends on the application - whether speed or accuracy (i.e., number of bits) is required.

Flash Convertors

Single/Dual Slope Integration Model

Successive Approximation/Tracking ADC